Integrated circuit having arbitrated switching between busses

ABSTRACT

An integrated circuit ( 1 ) includes a processing device ( 2 ), a program interface ( 4, 5 ) coupled to the processing device ( 2 ), a data interface ( 6, 7 ) coupled to the processing device. The program interface ( 4, 5 ) includes a first address bus ( 4 ) and a first data bus ( 5 ) and the data interface ( 6, 7 ) includes a second address bus ( 6 ) and a second data bus ( 7 ). The integrated circuit also includes address and data bus switching devices ( 18 ) and a control device ( 16 ). The address bus switching device ( 18 ) is coupled to the first and second address buses ( 4, 6 ) and adapted to be coupled to an external address bus ( 11 ) and the data bus switching device ( 18 ) is adapted to be coupled to an external data bus ( 12 ) and is coupled to the first and second data buses ( 5, 7 ). The control device ( 16 ) is coupled to the processing device ( 2 ), the address bus switching device ( 18 ) and the data bus switching device ( 18 ). The control device ( 16 ) controls the address and data bus switching devices ( 18 ) to couple the first address bus ( 4 ) and the first data bus ( 5 ) to the external address and data buses ( 11, 12 ) or to couple the second address bus ( 6 ) and the second data bus ( 7 ) to the external address and data buses ( 11, 12 ), in response to control signals received from the processing device ( 2 ).

The invention relates to an integrated circuit comprising processingdevice, such as a micro controller or micro processor.

Digital signal processors (DSP), such as those in modem chips, commonlyinclude a program interface and a data interface. The program interfacecomprises an address bus and a data bus and the data interface alsocomprises another address bus and another data bus. Each of the fourbuses will normally have 16 parallel lines. Hence, if each of the fourbuses is required to connect to a memory, or other device, outside ofthe integrated circuit in which the DSP is located, a pin for each lineon each bus is required. Typically, three pins are also required forcontrol signals. Hence, the total number of pins required on theintegrated circuit to communicate with the DSP is 70 pins. As a largeelement of the cost of producing integrated circuits is dependent on thenumber of pins required by the integrated circuit to communicate withexternal devices, the provision of 70 pins results in an expensiveintegrated circuit.

One method of reducing the number of external pins is to locate morememory devices on the integrated circuit itself to reduce therequirement of the DSP to communicate with external devices. However,memory tends to be expensive and to incorporate large memory capacitiesonto an integrated circuit is expensive. There is also the disadvantagethat the memory cannot be upgraded without replacing the entireintegrated circuit, including the DSP and other components which may notrequire to be upgraded.

Therefore, it is desirable to locate the memories outside of theintegrated circuit on which the DSP is located to permit memories to beeasily upgraded.

A solution to reduce the number of pins for communicating with theprogram interface and data interface of the DSP, while maintainingmemory devices outside the integrated circuit, is to couple the data andprogram address buses to an internal switching device within theintegrated circuit which can couple either of the address buses to anexternal address bus and similarly couple the data buses to anotherswitching device which permits either one of the data buses to becoupled to an external data bus.

Although this solution reduces the number of pins on the integratedcircuit, it has the disadvantage that it requires firm ware on theintegrated circuit to control the switching devices. In addition, theswitching devices can only be switched when the buses are not in use andfurthermore, a number of clock cycles are required to perform theswitching operation. Hence, for example, if the buses for the programinterface are coupled to the external address and data buses, theswitching devices can only switch the data interface buses to theexternal address and data buses after the program interface has finishedusing the external address and data buses. After the program interfacehas finished using the external address and data buses, a number ofclock cycles are required before the data interface can commence use ofthe external address and data buses.

Therefore, although the cost of the packaging is reduced for theintegrated circuit by reducing the number of pins, the speed at whichthe DSP can access the external memories is limited by the switchingtime, and that only the program interface or the data interface can becoupled to the external address and data buses at any one time.

In accordance with the present invention, an integrated circuitcomprises a processing device; a program interface coupled to theprocessing device, the program interface comprising a first address busand a first data bus; a data interface coupled to the processing device,the data interface comprising a second address bus and a second databus; an address bus switching device adapted be coupled to an externaladdress bus, the address bus switching device coupled to the first andsecond address buses; a data bus switching device adapted to be coupledto an external data bus, the data bus switching device coupled to thefirst and second data buses; and a control device coupled to theprocessing device, the address bus switching device and the data busswitching device, the control device controlling the address and databus switching devices to couple the first address bus and the first databus to the external address and data buses or to couple the secondaddress bus and the second data bus to the external address and databuses, in response to control signals received from the processingdevice.

An advantage of the invention is that by providing an integrated circuitwith a processing device and a control device coupled to the processingdevice and to the data and address bus interfaces, it is possible toswitch the external data and address buses between the program interfaceand the data interface during the same clock cycle.

Preferably, the control device comprises arbitration means whichprioritises requests for coupling to the external address and data busesfrom the program interface and the data interface. Typically, thearbitration means allocates priority to the program interface.

Preferably, the control device further comprises a delay generationmeans which generates a delay signal which the control device sends tothe processing device to prolong a processing device cycle to correspondto an access speed of an external memory being accessed by theprocessing device through the data and address bus switching devices.

Preferably, the delay generation means generates delays which are amultiple of the processing device fundamental clock cycle period.

An example of an integrated circuit in accordance with the inventionwill now be described with reference to the accompanying drawings, inwhich:

FIG. 1 is a schematic view of an integrated circuit having a digitalsignal processor and incorporating a common bus interface unit;

FIG. 2 is a schematic diagram showing a simplified architecture of thecommon bus interface unit;

FIG. 3 is a state table for the common bus interface unit shown in FIG.2;

FIG. 4 shows a first state diagram for the common bus interface unit;

FIG. 5 shows a second state diagram for the common bus interface unit;

FIG. 6 shows a third state diagram for the common bus interface unit;and

FIG. 7 shows a schedule of events for a program read and data writeoperation for the integrated circuit shown in FIG. 1.

FIG. 1 shows an integrated circuit 1 which includes a digital signalprocessor (DSP) 2 and common bus interface unit (C-BIU) 3. The DSP 2 hasa program interface which includes a program address bus (PA) 4 and aprogram data bus (PD) 5. The DSP 2 also has a data interface whichcomprises a data address bus (DA) 6 and a data data bus (DD) 7. Theaddress and data buses 4, 5, 6, 7 are coupled to the C-BIU 3 as well asto internal memory devices (not shown) also located on the integratedcircuit 1. A DSP control signal bus 8 supplies control signals from theDSP 2 to the C-BIU 3. The C-BIU 3 can send a non-maskable interruptsignal 9 to the DSP 2 and a wait signal 10 to the DSP 2.

The C-BIU 3 is also coupled to a common address bus (CA) 11 and a commondata bus (CD) 12, and can supply control signals to the common addressand data buses 11, 12 via a common bus control bus 13.

In addition, the C-BIU 3 can be coupled to a host processor (not shown)via a host bus 14 and a host control bus 15.

The common address and data buses 11, 12 enable the integrated circuit 1and in particular, the DSP 2, to communicate with devices, such asmemory devices located outside the integrated circuit 1.

A simplified architecture of the common bus interface unit 3 is shown inmore detail in FIG. 2. The main units of the C-BIU 3 are a busarbitration and control unit 16 and a wait state generator 17. The busarbitration and control unit 16 controls a multiplexer/tri-state buscontrol 18 which switches the appropriate buses 4-7 to the commonaddress and data buses 11, 12 in response to control signals receivedfrom the bus arbitration and bus control unit 16. In addition, the busarbitration and control unit 16 can control the multiplexer/tri statebus control 18 to which the common address and data buses to host bus 14via a host controller 19. The bus arbitration and control unit 16receives control signals from the DSP on the control signal bus 8 andalso receives inputs from a data address decoder 20, a host mail boxaddress 21, a program address decoder 22, program configurationregisters 23 and data configuration registers 24. The data addressdecoder 20, the host mail box 21, the program configuration registers 23and the data configuration registers 24 all receive inputs from the dataaddress bus 6. The program address decoder 22 receives an input from theprogram address bus 4.

As well as controlling the multiplexer/tri state bus control 18, the busarbitration and control unit 16 also controls the common buses 11, 12using a control signal bus 13 and communicates with the wait stategenerator 17 as well as instructing a non maskable interrupt generationunit 25.

The host which communicates with the C-BIU 3 via host bus 14 and thehost control bus 15 may be processor, micro controller or any otherexternal device which interfaces with the integrated circuit 1.

The program configuration registers 23 and the data configurationregisters 24 are programmable by the DSP 2 via the data address bus 6and provide integer values N, M respectively to the bus arbitration andcontrol unit 16. The integer values of N and M are dependent on theexternal memory being accessed. For example, for high performancememories the values of N and M will typically be low numbers. However,for low cost, low performance memories, the N and M values willtypically be high. The bus arbitration and control unit 16 controls thewait state generator 17 to generate a wait state in response to the Nand M values. Where the N and M values are low integers, the wait stategenerated by the wait state generator 17 will also be low and where theN and M values are high integers, the wait state generated by the waitstate generator 17 will also be high. The wait state generated by thewait state generator extends the fundamental clock cycle of the DSP 2 byan additional time period of one fundamental clock cycle for each waitstate generated. This is described in more detail below.

The C-BIU 3 also includes a program ROM protection unit 26. The programROM protection unit 26 disables program access to external memory toprotect the program available to the user.

In addition, the C-BIU 3 also includes an auto-incrementor 27. Theauto-incrementor 27 is activated by host access on the host bus 14 andhost control bus 15 via the host controller 19 and automaticallyincrements the address on the common address bus 11 for program downloadby the host. This feature reduces the number of cycles required todownload the program to external memory interface so that the host needsto send only the data over the demultiplexed host interface to bedownloaded to the external memory without requiring to supply anaddress, as this is automatically generated by the auto-incrementor 27.

The data address decoder 20 and the program address decoder 22 decodethe address range from the requested access by the DSP 2, check from theconfiguration registers whether the address has been enabled and alsodetermine the necessary program read, program write, data read and datawrite operations.

The non-maskable interrupt generation unit 25 could be generated to theDSP for every access to external memory.

In the event that the DSP 2 requests a program access operation, asignal P from the program address decoder 22 to the bus arbitration andcontrol unit 16 and the wait state generator 17 will go high to indicatethe DSP 2 is requesting a program access operation. If the DSP 2requests a data access operation, the data address decoder 20 willdetect this and a high signal D will be input to the bus arbitration andcontrol unit 16 and the wait state generator 17 to indicate that the DSP2 is requesting a data access operation.

The number of wait states generated by the wait state generator 17 willdepend on the values of N and M and also the requirements determined bythe bus arbitration and control unit 16 from the P and D signals fromthe program address decoder 22 and the data address decoder 20,respectively.

Typically, the integers N and M may be any integers from 0 to 15.

FIG. 3 shows an example of a state table for the C-BIU 3 where thevalues P and D refer to signals P and D from the data address decoder 20and the program address decoder 22, and W refers to the number of waitstates programmed in the wait state generator 17. The terms “one cycle”,“two cycle”, “three cycle” and “four cycle” refer to the number of DSPfundamental clock cycle periods over which the relevant operationoccurs. One cycle is equal to a wait signal 10 of 0 (i.e. 0 wait state),two cycles are equal to a wait signal 10 of 1 (i.e. 1 wait state), threecycles are equal to a wait signal 10 of 2 (i.e. 2 wait states). Hence,the extended cycle, which is the number of fundamental clock cycleperiods over which an operation takes place is equal to the value of thewait signal 10 (i.e. the number of wait states) plus 1.

In the case where W=0, P=0 and D=0 there is no program or data operationrequiring external access, therefore no wait state is generated and theDSP clock cycle is not extended. If W=0, P=0 and D=1, the busarbitration and control unit 16 recognises from the D=1 signal that theDSP 2 requires an external data read or write operation on the commonbuses 11, 12. Accordingly, to allow for external memory access times,the bus arbitration and control unit 16 instructs the wait stategenerator 17 to send a wait signal 10 to the DSP 2 to prolong thecurrent clock cycle to twice the fundamental clock cycle period, i.e. 1wait state is generated by the wait state generator 17. If P=1 and D=0,the bus arbitration and control unit 16 recognises that the DSP 2requires a program read or write operation using the common buses 11, 12and does not instruct the wait state generator 17 to generate a waitsignal 10 to the DSP 2.

If P=1 and D=1, the bus arbitration and control unit 16 recognises thatthe DSP 2 requires to make a program read or write operation and a dataread or write operation. The bus arbitration and control unit 16determines that it will not be possible to do this operation using thecommon buses 11, 12 and one fundamental clock cycle period. Therefore,the bus arbitration and control unit 16 instructs the wait stategenerator 17 to send a wait signal 10 with a value=2 (i.e. 2 waitstates) to extend the current clock cycle to three times the length ofthe fundamental clock cycle period.

The bus arbitration and control unit 16 is also programmed to prioritisebetween data and program accesses. In this example, the bus arbitrationand control unit 16 is programmed to give priority to programoperations. As shown in FIG. 4, the program read operation occurs in thefirst part of the cycle, then the data read or write operation occursduring the second part of the cycle.

Situations where the wait state register is programmed for 1 or greaterthan 1 wait state (i.e. W=1) are shown in the lower half of the table inFIG. 3 and the second and third state diagrams shown in FIGS. 5 and 6.FIG. 5 shows the state diagram for N=M, and FIG. 6 shows the statediagram for N≠M.

In FIG. 5, when P=0 and D=0 there is no program or data operation on thecommon bus and the wait state generator 17 does not generate any waitsignals 10 to prolong the DSP clock cycle. In the condition where D=1the bus arbitration and control unit 16 detects that the DSP 2 requiresa data read or write operation using the common buses 11, 12.Accordingly, the bus arbitration and control unit 16 instructs the waitstate generator 17 to generate one wait state to extend the current DSPclock cycle to twice the fundamental clock cycle period to ensure thatthe clock cycle is sufficiently long to permit the external memory to beaccessed and the data read or write operation to be performed.

Where P=1 and D=0, the bus arbitration and control unit 16 detects thatthe DSP 2 requires to use the common buses 11, 12 for a program read orwrite operation and instructs the wait state generator 17 to generateone wait state to the DSP to extend the current DSP clock cycle by anadditional fundamental cycle. This ensures that the DSP has sufficienttime to perform the program read or write operation in one cycle.

If P=1 and D=1, the bus arbitration and control unit 16 detects that theDSP requires to carry out both a program read or write operation and adata read or write operation, and instructs the wait state generator 17to generate a wait signal 10 of value=3 (i.e. 3 wait states) to the DSPto prolong the current DSP clock cycle to four times the length of theDSP fundamental clock cycle period. The bus arbitration and control unit16 also prioritises the operation and gives priority to the program reador write operation which, as shown in FIG. 5, occurs during the firstpart of the extended clock cycle and the data read or write operationoccurs during second part of the extended clock cycle.

For all the write operations, the write signal to the external memory isalways generated for N−½ cycle for program write or M−½ cycle for datawrite. This is important to ensure that data corruption does not occurdue to a change in clock cycle when the write takes place.

The third state diagram (FIG. 6) shows the state diagram for N=1, M=2and W=1, i.e. N and M have different values.

When there are no program or data operations required on the commonbuses 11, 12, P=0 and D=0 and no additional wait state generationrequired. Where P=0 and D=1, 2 wait states are generated, as M (whichcorresponds to the D signal) equals 2, so the wait state generator 17generates a wait signal 10 of value=2 to instruct the DSP 2 to extendthe clock cycle to three times the DSP fundamental clock cycle period.The data read or write operation occurs using the extended cycle.

When P=1 and D=0, the wait state generator 17 generates 1 wait state, asN (which corresponds to the P signal) equals 1. This extends the currentDSP clock cycle to twice the DSP fundamental clock cycle period so thatthe program read or write operation can occur during the extended cycle.

When P=1 and D=1, this means that the DSP requires the common buses 11,12 for both a program read or write operation and a data read or writeoperation. The bus arbitration and control unit 16 therefore, generatesN+M+1 wait state, which in this example is equal 4, to instruct the DSP2 to extend the current clock cycle to five times the DSP fundamentalclock cycle period. As priority is given to program operations, theprogram read or write operation occurs during the first portion of theextended clock cycle and the data read or write operation occurs duringsecond portion of the extended clock cycle.

An example of the scheduling of a program read and data write operationis shown in FIG. 7. In this example W=0, P=1 and D=1 and corresponds tothe first state diagram shown in FIG. 4. The bus arbitration and controlunit 16 detects that the DSP wishes to make a program read and a datawrite operation using the common buses 11, 12. The bus arbitration andcontrol unit 16 therefore instructs the wait state generator 17 to senda wait state signal 10 to the DSP to extend the current clock signal tothree times the DSP fundamental clock cycle period. The bus arbitrationand control unit 16 then switches the multiplexer/tri-state buscontroller 18 to couple the common buses 11, 12 to the program addressand data buses 4, 5 and sends a read control signal 100 on the controlbus 13. The program address 0040 is then sent through the programaddress bus 4 and the common address bus 11 to the selected memorydevice and the data 062C is retrieved from the memory device location0040 via the common data bus 12, through the common bus interface unit 3to the program data bus 5 and the DSP. After the program read operationhas been completed, the bus arbitration and control unit 16 thenswitches the multiplexer/tri-state controller 18 to couple the commonbuses 11, 12 to the data address and data buses 6, 7. The DSP thenaccesses memory location B003 by sending this location through the dataaddress bus 6 via the common bus interface unit 3 to the common addressbus 11 which accesses the memory B003.

Subsequently, data 45C0 is sent by the DSP 2 on the data data bus 7 tothe common data bus 12 via the common bus interface unit 3. The busarbitration and control unit 16 then sets a write signal 102 on thecommon bus control signal bus 13 to write data 45C0 to memory locationB003. The standard clock signal then finishes after the program read anddata write operations have been completed during the extended clockcycle.

In addition, program read or write and data read or write operations canbe performed using the host interface in a similar manner.

Hence, the invention has the advantage that by extending the DSP clocksignal it is possible to perform both a program read and data writeoperation during an extended clock signal by using the bus arbitrationand control unit 16 to control switching of the common buses 11, 12 tothe program or data interfaces.

There is also the advantage that firm ware is not required to configurethe interface and handle switching of the program and data interfaces tothe common buses.

The use of a wait state generator also has the advantage that itincreases the flexibility of the external memory devices with whichprocessors or micro controllers, such as a DSP 2, can access. It alsopermits access time to be configured according to the performance of thememory being accessed and reduces the requirement for read only memoryand or random access memory to be located on the same integrated circuitas the processor or micro controller.

What is claimed is:
 1. An integrated circuit comprising a processingdevice; a program interface coupled to the processing device, theprogram interface comprising a first address bus and a first data bus; adata interface coupled to the processing device, the data interfacecomprising a second address bus and a second data bus; an address busswitching device adapted to be coupled to an external address bus, theaddress bus switching device coupled to the first and second addressbusses; a data bus switching device adapted to be coupled to an externaldata bus, the data bus switching device coupled to the first and seconddata buses; and arbitration means coupled to the processing device, theaddress bus switching device and the data bus switching device, thearbitration means controlling the address and data bus switching devicesto couple the first address bus and the first data bus to the externaladdress and data buses or to couple the second address bus and thesecond data bus to the external address and data buses, in response tocontrol signals received from the processing device by allocatingpriority to the program interface over the data interface for couplingto the external address and data busses.
 2. An integrated circuitaccording to claim 1, wherein the arbitration means comprises a delaygeneration means which generates a delay signal which is sent to theprocessing device to prolong a processing device clock cycle inaccordance with an access speed of an external memory being accessed bythe processing device through the data and address bus switchingdevices.
 3. An integrated circuit according to claim 2, wherein thedelay generation means generates delays which are a multiple of theprocessing device fundamental clock cycle period.
 4. An integratedcircuit according to claim 2, wherein the length of the delay generatedby the delay generation means is dependent on whether the processingdevice request a program read or write operation, a data read or writeoperation or both a program and a data read or write operation to anexternal memory device.
 5. An integrated circuit according to claim 4,wherein in the case in which the processing device requests both aprogram and a data read or write operation to an external memory deviceduring a clock cycle, the arbitration means allocates priority to theprogram interface over the data interface for coupling to the externaladdress and data busses.